The present disclosure is generally directed to techniques for maintaining consistency between address translations and, more specifically to techniques for maintaining consistency between address translations in a memory management unit and an inclusive accelerator unit of a data processing system.
A memory management unit (MMU) is a hardware unit that translates virtual memory addresses to physical memory addresses. Modern MMUs typically divide a virtual address space (i.e., the range of addresses used by a processor) into pages that each have a size that is a power of two. The least significant bits of an address (i.e., the offset within a page) define the size of a page and are left unchanged. The most significant address bits provide a virtual page number. Most MMUs implement a page table, in main memory, that includes one page table entry (PTE) per page. The PTEs are used to map virtual page numbers to physical page numbers in main memory. An associative cache of PTEs, usually referred to as a translation lookaside buffer (TLB), may be maintained in order to avoid the necessity of accessing main memory every time a virtual address requires mapping. A PTE may also include information about whether a page has been written to, when the page was last used, what kind of processes may read and write the page, and whether the page should be cached.